The Most Expensive Millimetre in Photonics

If you have been following this publication from its earliest posts, you know that the platform we are building has two conceptual pillars. The first is the world of specialty optical fibers — large mode area designs, hollow-core photonic crystal fibers, anti-resonant waveguides. The second is the world of silicon photonics — nanoscale waveguides, ring modulators, programmable meshes, quantum photonic processors on chip. These two worlds were covered separately in the founding series because they are physically and technologically distinct domains.

But they are not isolated. Every time a silicon photonic chip needs to send or receive light from the outside world — from a laser source, from a sensing environment, from a quantum network, from a data center fiber link — it must interface with an optical fiber. And that interface, that single millimetre where light must transfer from a 10-micron fiber mode to a 300-nanometer silicon waveguide mode, is one of the most persistently difficult engineering problems in integrated photonics.

It is the problem that a paper published April 15th 2026 in AIP Advances, from Xinchao Zhou, Tzu-Han Chang, Eric Liu, Saivirinchi Prabandhakavi, and Chen-Lung Hung, addresses with a design that is notable for combining high performance with genuine fabrication simplicity. The title — “On-chip optical fiber-to-nanophotonic waveguide adiabatic coupler” — is technically precise to the point of being deliberately understated. What it describes is a solution to a problem that has constrained the practical deployment of nanophotonic systems for over two decades.

Why the Interface Is So Hard

To understand what makes this paper’s contribution meaningful, it helps to appreciate the scale of the problem it is solving.

A standard single-mode optical fiber — the kind that carries data across continents and connects data center racks — has a mode field diameter of approximately 10 micrometres at 1550nm wavelength. The optical field is relatively large, slowly varying, and well-matched to the gaussian beam profile of most free-space optics.

A silicon nanophotonic waveguide — the kind that routes light on a silicon photonic chip — has a cross-section of roughly 450nm × 220nm. The mode is tightly confined, with dimensions smaller than the wavelength of the light it carries, and the refractive index contrast between silicon (n ≈ 3.47) and its oxide cladding (n ≈ 1.44) is enormous by optical standards.

The mode field diameter mismatch between these two structures is approximately 30:1 in linear dimension, or roughly 1000:1 in area. Attempting to couple light directly from fiber to chip at an abrupt interface loses the vast majority of the optical power to radiation. This is not an imperfection in the manufacturing — it is a fundamental consequence of trying to couple two structures with modes of completely different spatial scales.

Three engineering approaches have been developed over the decades to manage this mismatch. End-fiber coupling, diffraction grating-based coupling, and adiabatic coupling each operate on different physical principles and involve different practical trade-offs. Grating couplers are by far the most commonly used — they are fabricated directly on the chip surface, require only vertical illumination from an optical fiber held above the chip, and are straightforward to integrate into standard PDKs. But grating couplers have limited optical bandwidth and are naturally out-of-plane, which creates both wavelength selectivity constraints and packaging complexity for edge-connected systems.

Adiabatic coupling is the physically elegant alternative. In adiabatic mode transfer, single-mode fiber-waveguide coupling efficiencies as high as 97% are achievable. Efficient coupling is obtained for a wide range of device geometries which are either singly-clamped on a chip or attached to the fiber, demonstrating a promising approach for integrated nanophotonic circuits, quantum optical and nanoscale sensing applications.

The word “adiabatic” here is borrowed from thermodynamics but applied to optics: a transformation is adiabatic if it happens slowly enough that the system remains in its fundamental mode throughout. In an adiabatic coupler, both the fiber and the waveguide are tapered — one getting narrower, the other getting wider — over a sufficient length that the optical mode transitions smoothly from one structure to the other without exciting higher-order modes or radiation modes. No abrupt interface. No mode mismatch loss. Just a gentle, gradual handover of the optical field.

The challenge with adiabatic couplers has always been fabrication. The problem of fiber-to-chip coupling is difficult because the fundamental mode of an optical fiber is roughly 10 µm in diameter, and the dimensions of the fundamental mode of a high-index-contrast waveguide are often less than 1 µm across. Earlier demonstrations of adiabatic coupling required either substrate releasing — a delicate microfabrication step that suspends the waveguide in air to prevent light leakage into the substrate — or cladding the tapered fiber tip in a higher-index polymer material to prevent the field from leaking before it reaches the chip waveguide. Both approaches add fabrication complexity and reduce yield.

What the New Design Actually Does

The AIP Advances paper reports a simple design of an on-chip fiber-to-nanophotonic waveguide adiabatic coupler. An inverse-tapered waveguide can be fabricated on an etched oxide layer to achieve index-crossing with a tapered optical fiber without severe light leakage into the substrate. The design involves simple fabrication steps without substrate releasing and does not rely on cladding the tapered fiber in a higher-index material.

The key innovation is the combination of two elements that have individually appeared in the literature but not been combined in this specific way. The first is the inverse taper on the chip side — a waveguide that deliberately narrows toward the fiber interface, reducing its effective index until it matches the effective index of the tapered fiber at the coupling point. The second is the etched oxide layer that creates a local region where the waveguide is suspended above a lower-index medium, preventing the evanescent tail of the guided mode from leaking into the substrate during the index-crossing event.

The index-crossing condition is the physical heart of the design. As the chip waveguide tapers down and the fiber tapers down simultaneously, there is a specific geometric point — a crossover — where the effective index of the chip mode and the effective index of the fiber mode become equal. At this point, the modes are phase-matched, and adiabatic power transfer from fiber to chip occurs naturally. The etched oxide ensures that this crossover happens cleanly, without the substrate acting as a lossy competing waveguide that steals power during the transition.

The simulated transmission efficiency reaches beyond 95% (−0.2 dB) with robust alignment tolerance for quasi-transverse magnetic polarization. The coupler shows reasonably wide bandwidth and high coupling efficiency for both fundamental quasi-TM and quasi-TE polarizations.

−0.2 dB insertion loss is an exceptional result. For context: state-of-the-art grating couplers typically achieve −1.5 dB at their peak wavelength. Standard edge couplers with lensed fibers achieve approximately −1.1 dB. The silicon chip is fabricated at a commercial foundry and then post-processed to release the tapering nanowires in some competing designs — a process step that this paper explicitly eliminates. The result is a coupling efficiency that rivals the best demonstrated adiabatic couplers, achieved with a fabrication process that is compatible with standard silicon photonic foundry workflows.

The alignment tolerance is the other critical metric. Any fiber-to-chip coupling scheme that requires sub-micron alignment precision becomes expensive to package at production scale — each chip requires active alignment under illumination, consuming operator time and specialised equipment. Adiabatic couplers are conducive to high-bandwidth, low-loss operation because neither mode matching nor k-vector matching at an abrupt interface occurs, so loss can be low across a broad bandwidth without high sensitivity to position. The AIP Advances design inherits this alignment robustness by design.

The Platform Connection — Why This Paper Matters Here

The coupling problem this paper solves sits at the exact boundary between the two technology domains that the Precision with Light platform is designed to bridge.

Every silicon photonic design that leaves this platform — every inverse-designed waveguide, every optimised ring modulator, every quantum photonic processor layout — eventually needs to connect to the outside world through an optical fiber. The coupler is not an afterthought in the PIC design flow. It is a first-class component that must be co-designed with the rest of the circuit, because its mode profile at the chip interface constrains the waveguide geometry on chip, and its taper length and oxide etch depth must be compatible with the foundry PDK.

For the platform specifically, this paper establishes three design parameters that belong in the fabrication constraint database for any edge-coupled silicon photonic design:

The inverse taper tip width — the narrowest point of the on-chip waveguide at the coupling interface — is the critical dimension that determines whether the effective index crossing condition is met. For a 220nm SOI platform, this tip width typically falls in the range of 80–150nm, which is at or below the resolution limit of standard 193nm deep-UV lithography. This is a hard DRC constraint that the DSR-CRAG system must enforce: a generated waveguide design that proposes a taper tip narrower than the foundry’s minimum printable feature fails before simulation.

The oxide etch depth — the thickness of silicon dioxide removed beneath the inverse taper to create the suspended region — is a process parameter that varies between foundries and imposes a constraint on the waveguide height above substrate during the coupling transition. This parameter connects the optical design directly to the process chemistry, which is precisely the kind of cross-layer constraint that the platform’s multi-level PINN framework is designed to propagate.

The coupling length — the distance over which the adiabatic transition occurs — is the design parameter that trades off device footprint against coupling efficiency and bandwidth. Shorter coupling lengths are more compact but less adiabatic, introducing mode conversion loss. For a co-packaged optics PIC where chip area is at a premium, the coupling length is an optimisation variable, not a fixed parameter. This is exactly the kind of multi-objective problem — minimise footprint, maximise efficiency, maintain bandwidth — where inverse design outperforms manual parameter sweeps.

The Broader Picture: Fiber Meets Silicon

This paper is in one sense a very specific technical contribution — a coupler design, simulated to 95% efficiency, with a simplified fabrication process. In another sense it is a data point in a larger story that this publication has been tracking.

The history of photonics over the past three decades can be read as a progressive integration of functions that were once performed by discrete fiber components — lasers, amplifiers, modulators, splitters, sensors — onto silicon photonic chips. Each integration step has required solving the same fundamental problem at smaller scale: how do you get light from the world of glass into the world of silicon, and back again, without losing it at the boundary?

The adiabatic coupler is one answer to that question, and this paper advances it meaningfully. But the deeper implication is that the boundary between fiber photonics and silicon photonics is not a wall — it is an interface, and interfaces can be engineered. The platform we are building treats fiber design and silicon photonic design as two modules of the same system, connected through exactly the kind of coupler that this paper describes.

When a user of the platform specifies “I need a silicon photonic gas sensor operating at 2 microns, fiber-coupled, with less than 0.5 dB total coupling loss,” the design problem spans both domains simultaneously: the PCF fiber design delivering the probe light, the edge coupler translating it from the fiber mode to the chip mode, and the on-chip waveguide routing it to the sensing region. None of those three components can be designed independently. The coupler is the connecting tissue.

Papers like this one are the building blocks of that integrated design capability.

We just end by displaying here the Conclusions paragraph we can read in the paper, which validates our points in the author’s own language:

In summary, we present a simple design and fabrication study of an on-chip tapered optical fiber-to-nanophotonic waveguide adiabatic coupler. The coupling efficiency, estimated via an FDTD simulation, could already reach 95% transmission for the fundamental quasi-TM mode without exhaustive search of optimal geometric parameters. The adiabatic coupler is expected to be broadband with less than a 3 dB drop for 300 nm around the design wavelength. The design features high coupling efficiency also for quasi-TE polarization. We investigate the effect of substrate etching and find that the resulting design achieves high coupling efficiency at the target wavelength. The key principle is to engineer a refractive-index crossing to satisfy the adiabatic condition. We believe that this design approach can be readily adapted to integrated photonic platforms coupled with other quantum emitters of nearby transition wavelengths, such as quantum dots and defect color centers.

Paper reference: Zhou, X., Chang, T.-H., Liu, E., Prabandhakavi, S., & Hung, C.-L., "On-chip optical fiber-to-nanophotonic waveguide adiabatic coupler," AIP Advances 16, 045315 (2026). → https://doi.org/10.1063/5.0322573

Nuno Edgar Nunes Fernandes Precision with Light precisionwithlight.substack.com · GitHub

The Quiet Failure Mode

There is a class of engineering error that is more dangerous than an obvious error. It is the error that looks correct.

A finite element simulation that fails to converge produces obvious warnings. A solver that runs out of memory crashes visibly. But a neural network that has learned a subtly wrong mapping — one that produces geometrically plausible, numerically reasonable outputs that happen to violate the underlying physics — fails quietly. It produces a number. The number has units. It falls within the expected range. And it is wrong in a way that no downstream check will catch unless you know exactly what to look for.

In most domains of machine learning, this kind of quiet failure is a recoverable problem. A spam filter that misclassifies some emails can be retrained. A recommendation system that surfaces the wrong content can be corrected with user feedback. The cost of a wrong prediction is low and the correction loop is fast.

In photonics design, the cost of a wrong prediction is a foundry run.

A silicon photonic chip tapeout at a commercial foundry costs between $5,000 and $50,000 depending on the process node and whether you are sharing a Multi-Project Wafer with other users. The fabrication cycle takes eight to sixteen weeks. If the design is wrong — if the ring modulator’s resonant wavelength is shifted by 2nm because the effective index was predicted incorrectly, if the directional coupler’s splitting ratio is 60:40 instead of 50:50 because the coupling gap was off by 20nm, if the grating coupler’s peak efficiency is at 1540nm instead of 1550nm because the period was slightly misspecified — you do not discover this until the chip comes back from the foundry and fails characterisation.

At that point, there is no fast correction loop. There is an eight-week respun design cycle.

This is why the question why should you trust an AI-generated photonic design? is not academic. It is the question that determines whether AI-assisted photonic design is a research curiosity or a production tool. And the answer, stated plainly, is: you should not trust a black-box neural network. You should trust a physics-informed neural network with solver-verified outputs. The difference is not a minor architectural detail. It is the entire design philosophy.

What Black-Box Means and Why It Fails

A “black-box” surrogate model, in the context of photonics design, is any neural network trained exclusively on input-output data — geometry parameters in, optical properties out — without any explicit encoding of the governing physical laws.

The canonical example in our corpus is the original PCF regressor: an MLP trained on a dataset of {pitch Λ, hole diameter d, wavelength λ} → {n_eff, mode area, dispersion, confinement loss} mappings generated by FEM simulation. The network learns the statistical relationship between inputs and outputs. It is fast, accurate within the training distribution, and genuinely useful.

The failure modes appear at the edges of the training distribution and in the physical consistency of the predictions.

Failure mode 1: Extrapolation without physical boundaries. A standard MLP will extrapolate outside its training distribution in ways that violate physical constraints. The most dangerous violation in fiber optics is predicting a real part of the effective index Re(n_eff) that exceeds the core material’s refractive index — physically impossible for a guided mode, which must satisfy n_clad < Re(n_eff) < n_core. A network that has never been explicitly constrained to respect this boundary will violate it in the tails of the parameter distribution, precisely where novel designs tend to live.

Failure mode 2: Topological discontinuities. In photonic crystal fibers, the design parameter space contains discontinuous boundaries between qualitatively different guidance regimes — index-guiding, photonic bandgap, and anti-resonant. Near these boundaries, small geometry changes produce large, non-smooth changes in the optical properties. A neural network that interpolates through these regions produces outputs corresponding to no physical solution. The network has no mechanism to detect that it has entered a topologically forbidden region of design space.

Failure mode 3: Multi-physics coupling. A thermal gradient in a silicon photonic chip shifts the refractive index of the waveguides through the thermo-optic effect (dn/dT ≈ 1.8×10⁻⁴ K⁻¹ for Si), which shifts resonant wavelengths, which changes the routing of wavelength channels across the chip. A purely data-driven model trained on room-temperature characterization data will mispredict the behavior of a chip running at 70°C junction temperature — which is the actual operating condition in a co-packaged optics module. Photonic-electronic-thermal co-simulation is not an optional refinement (reference publication link in the references section below). It is a requirement for CPO designs.

The general principle underlying all three failure modes is the same: a data-driven model has no mechanism to detect or penalize outputs that are internally inconsistent with the physical laws governing the system it is trying to model. It can only minimize the statistical error against its training data. Whatever the training data does not cover, the network cannot constrain.

Read more

Why Tensor Operations Are the Bottleneck

Every time a large language model generates a token, every time a computer vision system identifies an object, every time a scientific simulation runs a forward pass — the dominant computational operation is the same: a matrix-vector multiplication. Multiply a weight matrix by an input vector, accumulate the results, apply a nonlinearity, repeat hundreds of times per layer and thousands of layers deep.

At the scale of modern AI inference — GPT-class models, vision transformers, protein folding networks — this amounts to hundreds of billions to trillions of multiply-accumulate (MAC) operations per inference pass. The silicon doing this work is fast, but it is not free. Each MAC operation charges and discharges capacitors, moves electrons across resistive connections, generates heat, and consumes power. At data center scale, the aggregate energy cost of this is one of the defining infrastructure challenges of the next decade.

The photonic computing community has argued for years that there is a better way: perform the linear algebra in the optical domain, where signals travel at the speed of light, without resistive loss, without capacitive charging, and without electrical crosstalk. The argument is physically sound. The implementation challenge has been formidable.

A paper published April 9 2026 in Nature Communications, from a team at the Kirchhoff-Institute for Physics at the University of Heidelberg together with Enlightra — a Swiss microcomb startup — represents the most complete answer to that implementation challenge demonstrated to date. It is worth reading carefully.

What Was Actually Built

The paper presents a photonic tensor processor (PTP) that performs deep neural network inference using an all-optical crossbar architecture, packaged into a standard 19-inch rack unit with a high-speed electronic interface to PyTorch.

Let us be precise about what each of those elements means.

The crossbar: A 9×3 incoherent optical crossbar — nine inputs, three outputs. At each input, an electro-absorption modulator (EAM) encodes a vector element by modulating the intensity of an incoming light beam. At each intersection of the crossbar, a second EAM sets a weight by controlling how much of that intensity passes through. The modulated intensities from all nine inputs propagate to the three outputs, where on-chip SiGe photodiodes sum them through optical power accumulation — literally adding intensities — and convert the result to an electrical current. This is a parallel, all-optical matrix-vector multiplication.

The word “incoherent” is important. Most earlier photonic computing demonstrations used coherent architectures — Mach-Zehnder interferometer meshes where phase relationships between beams encode the computation. Coherent systems offer high precision but require tight phase control across the entire chip, which is difficult to maintain at scale. The Heidelberg group’s incoherent approach uses intensity, not phase — simpler to calibrate, more robust to fabrication variation, and more compatible with the kind of weighted optical power accumulation that maps naturally to neural network multiply-accumulate operations.

The light source: A self-injection-locked microcomb based on a high-Q Si₃N₄ microresonator, supplied by Enlightra. A microcomb generates a comb of equally spaced optical frequencies from a single pump laser — in this case with a 485 GHz free spectral range, producing multiple wavelength carriers simultaneously. Each wavelength channel carries one input of the nine-input vector in parallel. This wavelength-division multiplexing of the computation is one of the most elegant aspects of the architecture: rather than time-multiplexing the inputs sequentially, all nine inputs are processed simultaneously on different wavelength channels, and the photodiodes integrate across all wavelengths naturally.

The use of a microcomb as the source — rather than nine individually stabilised lasers — is not merely an engineering convenience. It is what makes the system practically deployable. Nine separate tunable lasers, each requiring active wavelength locking, would introduce a calibration and reliability burden that would dwarf the computational advantage. The SIL microcomb solves this in a single, packaged, low-noise source.

The silicon photonics platform: The chip is fabricated on imec’s iSiPP50G process — the same European silicon photonics foundry platform that appears in the co-packaged optics and programmable photonics discussions throughout this series. This is not an academic custom process. iSiPP50G is a production-accessible, multi-project-wafer platform with established design rules, a PDK, and a known yield profile. The fact that a photonic AI accelerator demonstrating state-of-the-art DNN inference was built on this platform is a strong signal about where the field is heading: toward foundry-compatible, replicable photonic computing hardware.

The electronic interface: A ZCU216 RFSoC FPGA running at 4 GS/s for EAM modulation and 2 GS/s for readout, connected to a Jupyter server via Ethernet, with direct PyTorch integration. The computational model is: the GPU or CPU runs the network up to a linear layer, offloads the matrix-vector multiplication to the photonic processor, receives the result, applies the nonlinearity digitally, and continues. The handoff is seamless from PyTorch’s perspective — the PTP appears as a hardware backend, not unlike how a GPU appears as a CUDA device.

Read more

The Wrong Question

Every simulation tool ever built for photonics answers the same question.

Given this geometry — this core diameter, this cladding structure, this refractive index profile — what does the light do?

It is a reasonable question. It is the question that COMSOL answers, that Ansys Lumerical answers, that RP Fiber Power answers. Run the finite element solver, apply Maxwell’s equations to the geometry you have defined, and the software tells you the mode profile, the loss, the dispersion, the nonlinear coefficient. Fast, accurate, trustworthy.

The problem is that it is the wrong question.

The question that engineers actually need answered is different. A biomedical imaging researcher doesn’t start with a fiber geometry and wonder what it does. They start with a clinical requirement — a 770nm probe beam for two-photon imaging through tissue — and ask: what fiber do I need to build? An industrial laser engineer doesn’t start with a waveguide cross-section and observe the dispersion profile. They specify a target: zero-dispersion wavelength at 1030nm, anomalous dispersion across the Yb gain bandwidth, confinement loss below 0.01 dB/km. Then they ask: what geometry produces this?

That is the inverse problem. And for thirty years of modern photonics engineering, it has had no software answer. The inverse problem belonged entirely to human intuition, accumulated domain knowledge, and exhaustive manual search through design space.

Until it doesn’t have to.

What Makes a Problem Invertible

To understand why inverse design is only now becoming practical, it helps to understand what makes a physical design problem tractable as a machine learning task.

Three conditions must hold.

The forward mapping must be learnable. The relationship between geometry and optical performance must be a well-defined function — not random, not chaotic, but a continuous mapping that a neural network can approximate. For photonic crystal fibers, the relationship between pitch Λ, hole diameter d, and operating wavelength λ on one side, and effective index n_eff, mode area A_eff, and dispersion D(λ) on the other, is exactly this kind of mapping. Nonlinear and high-dimensional, but continuous and learnable.

The design space must be searchable. There must be enough geometric variation, produced at reasonable computational cost, to build a training dataset. This is where the traditional FEM bottleneck has been a barrier. A single Lumerical FDTD simulation of a complex PCF geometry can take hours. A comprehensive training dataset requires tens of thousands of these simulations. The cost is prohibitive unless you have a supercomputing cluster and weeks of patience.

The physics must be enforced. A naive neural network will happily predict geometries that are faster to generate than physically valid. An n_eff that exceeds the silica refractive index. A dispersion curve that violates causality. A mode area that is geometrically impossible for the specified core radius. These “hallucinated” solutions are the central danger of applying machine learning to physics problems without appropriate constraints.

The sixth paper in the founding corpus — a 2023 paper from MDPI Photonics on inverse design of photonic crystal fibers for four-wave mixing — demonstrated that all three conditions can be satisfied simultaneously, and that the result is not just a faster version of the existing workflow. It is a categorically different capability.

The Four-Wave Mixing Proof

Four-wave mixing is a third-order nonlinear optical process. Two pump photons at frequency ω_p interact inside a fiber to generate a signal photon at ω_s and an idler at ω_i, conserving energy: 2ω_p = ω_s + ω_i.

The efficiency of this frequency conversion depends critically on phase matching — the condition that the wave vectors of all participating waves remain synchronized along the interaction length. In mathematical terms:

where γ is the nonlinear coefficient of the fiber and P is the pump power. The propagation constants β(ω) are themselves functions of the fiber’s dispersion profile D(λ), which is determined entirely by the fiber’s cross-sectional geometry.

The target application was biomedical imaging. The requirement: a 1064nm pump laser — widely available, commercially mature — generating a signal at exactly 770nm. That wavelength is not arbitrary. It sits in the first biological transparency window, where tissue scattering and water absorption are simultaneously minimized. It matches the excitation wavelength of specific fluorescent probes used in two-photon microscopy. It enables imaging depths and resolutions not achievable at longer wavelengths.

The engineering challenge: find a photonic crystal fiber geometry whose dispersion profile satisfies the phase matching condition for this specific pump-signal pair. In traditional practice, this means running hundreds of FEM simulations, computing D(λ) for each candidate geometry, checking whether the phase matching condition is satisfied, and iterating. Days of expert work, at minimum.

The paper’s approach was different. A deep neural network was trained on a library of geometry-to-dispersion mappings — thousands of PCF geometries, each characterized by its pitch, hole diameter ratio, and core structure, each paired with its numerically computed dispersion profile. Once trained, the network learned the inverse mapping: given a target dispersion profile that satisfies phase matching for the desired pump-signal pair, synthesize the PCF geometry that produces it.

Forward simulation time per geometry: hours. Inverse design inference time: under one millisecond.

The network produced a manufacturable PCF geometry whose dispersion profile, when verified by FEM, satisfied the phase matching condition for 1064nm → 770nm conversion. The result was not approximate. It was not a good starting point for further manual optimization. It was the answer.

Why This Is Not Just Speed

This is the profile of a senior optical engineer with a decade of specialist experience. Most photonics companies have one or two such people. Most academic research groups have one.

The temptation is to frame inverse design as an acceleration technology. Weeks become milliseconds. That framing is accurate but insufficient.

The more important consequence is that it changes who can design photonic devices.

With traditional FEM-based forward design, producing a novel PCF geometry for a specific application requires: familiarity with the FEM solver and its mesh convergence behavior, deep intuition about the geometry-performance mapping, access to expensive software licenses, and weeks of available time.

With inverse design, the workflow becomes: specify the target performance. Receive candidate geometries. Verify with a single forward simulation. The required expertise shifts from “how to navigate the design space” to “how to specify the target correctly.” A junior engineer with solid optics fundamentals can produce design candidates that previously required rare specialist knowledge.

This has a direct consequence for innovation velocity. If the design bottleneck is removed, the fabrication and characterization cycle becomes the rate-limiting step — and that cycle is already getting faster with MPW (Multi-Project Wafer) services and automated characterization platforms. The entire R&D pipeline accelerates.

The Physics Constraint Problem — And Why It Cannot Be Ignored

Inverse design without physics enforcement is dangerous in ways that are easy to underestimate.

A standard neural network trained to map optical targets to geometries will occasionally produce outputs that satisfy the training loss while violating physical reality. The three most common failure modes in photonics inverse design are:

Evanescent field violations. The predicted effective index Re(n_eff) exceeds the core material index — physically impossible, since guided modes must satisfy n_clad < Re(n_eff) < n_core. A network that has never been explicitly constrained to respect this boundary will violate it in corner cases of the parameter space.

Fabrication rule violations. The predicted geometry has feature sizes below the lithographic resolution limit of the target process. A sub-100nm air hole in a PCF cannot be reliably drawn with a stack-and-draw fabrication process. A ring resonator with a 2µm radius cannot be fabricated in AIM Photonics’ 300mm SOI process where the practical minimum is approximately 5µm. Geometries that ignore these rules are academically interesting and industrially useless.

Topological discontinuities. The network interpolates through a region of design space that corresponds to a discontinuous change in guidance mechanism — for example, from index-guiding to bandgap-guided operation in a PCF. The interpolated geometries in between are not physical solutions; they correspond to no stable guided mode. Standard neural networks cannot detect these discontinuities and will synthesize geometries that fall into them.

Physics-Informed Neural Networks (PINNs) address the first failure mode directly, by incorporating the residual of the governing wave equation into the training loss:

where L_physics is the norm of the Helmholtz equation residual evaluated at the predicted field and eigenvalue. A network that violates Maxwell’s equations is penalized during training, not just at inference time. The result is a model that has internalized the physics, not just approximated the data.

The second and third failure modes require a different mechanism: a design rule constraint database, queried before generation rather than after. This is the architectural innovation at the heart of the DSR-CRAG system that powers this platform — Dual-State Corrective Retrieval-Augmented Generation. When a design request arrives at the Intent Layer, the first operation is not generation. It is retrieval: pull the relevant fabrication constraints for the target process node, apply them as hard boundaries, and only then allow the generative engine to operate within the feasible space.

The difference between a generative AI that synthesizes photonic devices and one that synthesizes manufacturable photonic devices is this constraint layer. Without it, the platform produces interesting geometries. With it, it produces designs that can be taped out.

Inverse Design at the Silicon Photonics Scale

The fiber inverse design proof of concept is compelling, but fiber geometry is a relatively low-dimensional problem. The PCF design space is spanned by three to six continuous parameters, and the fabrication process is a single draw-tower operation. Silicon photonics design is more complex by an order of magnitude.

A silicon photonic integrated circuit involves dozens to hundreds of individual components — waveguides, bends, directional couplers, ring resonators, interferometers, grating couplers, modulators, photodetectors — each with its own geometry, each interacting with adjacent components through optical coupling and thermal crosstalk. The design space is not three-dimensional. It is effectively infinite.

A 2025 paper in Nature Communications demonstrated inverse design on the silicon nitride platform — the same Si₃N₄ material used by QuiX Quantum for their quantum photonic processors, and an increasingly important platform for both classical and quantum photonic integration. The results were striking: freeform inverse-designed devices achieved up to a 1,200× reduction in footprint compared to conventional designs, while maintaining minimum feature sizes of 160nm — well within the capability of standard photolithography. A wavelength-division multiplexer, a five-mode multiplexer, and a polarization beam splitter: three different device types, all compressed by three orders of magnitude in area, all fabricated and characterized successfully.

A 1,200× footprint reduction is not an incremental improvement. It is a qualitative change in what silicon photonic integration density is possible. It means functions that previously required a millimeter of waveguide length can be implemented in a micrometer. At the scale of a co-packaged optics switch PIC — carrying 16 channels, each at 200Gbps, on a chip that must fit within the thermal and area budget of a data center ASIC package — this kind of density improvement is the difference between feasible and infeasible.

The Process Design Kit: Physics Constraints Made Machine-Readable

There is one more layer of the inverse design story that rarely appears in academic papers but is essential to any platform that aims to produce real devices.

Process Design Kits — PDKs — are the machine-readable specifications that foundries provide to designers. A PDK encodes, in software, the complete set of constraints that a fabrication process imposes: minimum feature sizes, layer thicknesses, doping profiles, metal stack definitions, design rule checks. Every silicon photonic circuit that reaches a foundry does so through a PDK.

The current state of photonic PDKs mirrors the state of photonic simulation tools before inverse design: powerful, necessary, and requiring deep specialist knowledge to use. Different foundries provide PDKs in different formats, for different design tools, maintained by separate teams. The result is fragmentation: a design optimized for the AIM Photonics 300mm process cannot be trivially ported to IMEC iSiPP50G or IHP SG25H5 (EUROPRACTICE IC Service offers Multi-Project-Wafer (MPW) services and small volume production in high frequency SiGe:C BiCMOS from IHP in Europe) without reconstructing the constraint layers from scratch.

The OpenEPDA initiative — developed at TU Eindhoven and validated through the JePPIX European MPW consortium — is attempting to solve this with a standardized, software-independent PDK representation. One dataset from the foundry, compiled into any design tool’s native format. The approach has been validated with three foundries and four EDA tool vendors.

For the Precision with Light platform, OpenEPDA-compatible PDK ingestion is not a nice-to-have. It is the mechanism by which the DSR-CRAG constraint database stays current as foundry processes evolve. When AIM Photonics updates their process design rules — as they do with each process node revision — an OpenEPDA-formatted update is ingested, the constraint database updates automatically, and every subsequent design generated by the platform reflects the new rules. No manual constraint re-entry. No risk of designing to stale DRC rules.

The physics is enforced by the PINNs. The fabrication rules are enforced by the PDK. Together, they make the guarantee: every geometry this platform produces is not just physically valid, but foundry-ready.

What This Means for the Platform

The inverse design capability described in this post is not a feature of the Precision with Light platform. It is the platform’s core value proposition, stated precisely:

A system that takes optical performance targets as input, enforces hard physical and fabrication constraints before generation, synthesizes manufacturable geometries using physics-informed generative AI, and verifies the results against industry-standard solvers before delivery.

The FWM (Four-wave Mixing) paper demonstrated this for fiber photonics. The Nature Communications Si₃N₄ paper demonstrated it for integrated silicon photonics. The PDK standardization work provides the constraint layer that makes the generated designs foundry-ready. The multi-level PINN framework from the latest computational physics literature provides the architecture that prevents physical constraint violations during generation.

The pieces are all present. The platform assembles them.

What Comes Next

Post 3 — “From Glass to Qubits: Silicon Photonics, Co-Packaged Optics, and the Platform Under the Platform”: the data center AI infrastructure story, programmable photonic meshes, quantum photonic processors, and why the MPW batch endpoint changes the economics of photonics R&D.

Post 4 — “Why AI Needs Physics: The Case Against Black-Box Surrogates in Photonics Design”: the rigorous argument for physics-informed approaches, what the latest PINN methodology says about surrogate models you can actually trust, and the multi-fidelity simulation strategy that makes verification tractable.

Post 5 — “Open for Business”: the complete platform architecture, the partnership model, and how to get involved — whether as a research collaborator, an industry partner, or an academic institution seeking access.

Bear in mind that the Posts titles above may change when the time of writing, editing and posting arrives.

If inverse design is a problem space your team is working on — in fiber photonics, silicon photonics, or anywhere in the broader landscape of computational electromagnetics — I want to hear from you. The design software layer for the next decade of photonics is being built now.

Subscribe below to follow the series.

Nuno Edgar Nunes Fernandes Founder, Precision with Light precisionwithlight.substack.com · GitHub

The paper from Nature Photonics outlining the above mentioned achievements presents a novel approach to address the high energy and chip area demands of data transmission between semiconductor chips, a significant barrier for scaling artificial intelligence (AI) hardware. The authors introduce a solution based on dense three-dimensional (3D) integration of photonics and electronics.

Here's a more detailed breakdown of the paper's key aspects:

1. Introduction and the Bottleneck in AI Scaling:

• The paper begins by highlighting the revolutionary potential of AI hardware leveraging vast distributed networks of advanced semiconductor chips.

• However, a critical challenge for scaling AI is the disproportionately high energy and chip area required for inter-chip data transfer.

• Currently, electrical data within a chip needs to be converted to optical data for efficient transmission, often relying on centimetre-long electrical wires before interfacing with pluggable optical transceivers.

• This limited number of electrical channels and their wire lengths lead to data rates that are not easily scalable without substantial energy consumption.

2. The Proposed Solution: Dense 3D Photonic Integration:

• To overcome this bottleneck, the paper proposes and demonstrates a platform based on the dense 3D integration of photonics and electronics.

• Their platform achieves an order-of-magnitude-greater number of 3D-integrated channels compared to previous demonstrations, with 80 photonic transmitters and receivers occupying a combined chip footprint of only 0.3 mm².

• This high level of integration enables both high bandwidth (800 Gb s⁻¹) and highly efficient, dense (5.3 Tb s⁻¹ mm⁻²) 3D channels.

3. Key Performance Metrics:

• The transceiver exhibits state-of-the-art energy efficiency, with 50 fJ per bit for the transmitter front end and 70 fJ per bit for the receiver front end, operating at 10 Gb s⁻¹ per channel.

• The high density of channels compensates for the relatively lower per-channel data rate, resulting in a high aggregate data rate.

4. Technology and Fabrication:

• The design is compatible with commercial complementary metal–oxide–semiconductor (CMOS) foundries fabrication on 300-mm-sized wafers, providing a pathway to mass production.

• The integration leverages silicon photonics, a technology that can utilise the existing CMOS infrastructure for microelectronics fabrication. Silicon photonics allows for compact and efficient electrical-to-optical and optical-to-electrical conversions using devices like microresonator-based modulators, filters, and germanium photodiodes.

• Unlike monolithic integration of CMOS and photonics on the same 2D chip (which can limit benefits from advancements in CMOS nodes), this approach uses 3D integration, combining a leading-edge CMOS electronic chip and a separate photonic chip.

• The high density is achieved using a high-density bonding process with copper pillar bumps, featuring a 15 μm spacing and 10 μm bump diameters (25 μm pitch) in an array of 2,304 bonds. This bonding demonstrates a robust connection with low capacitance (10 fF per bond).

5. Transceiver Architecture and Performance:

• The 3D-integrated chip contains an array of 80 transmitter cells and 80 receiver cells, organised into 20 waveguide buses with four wavelength channels per bus.

• Each transmitter cell has local memory and uses voltage pulses to drive microdisk modulators, which modulate an on-resonance laser line. The vertical p–n junction microdisk enables low-voltage drive and achieves a significant resonance shift per volt. The transmitter cell consumes 50 fJ per bit with a 1 V swing.

• The receiver cells use microrings to selectively drop wavelengths onto photodiodes, converting the optical signals back to electrical current, which is then amplified and written into local memory. The receiver cell consumes 70 fJ per bit when receiving a 10 Gb s⁻¹ signal at a specific power level.

• The photodiode used is a vertical p-silicon, i-germanium, and n-germanium diode with high responsivity. Minimising the capacitance of this photodiode is crucial for reducing receiver noise and improving energy efficiency.

6. Data Communication Link Demonstration:

• The researchers demonstrated a complete data communication link by connecting two separate transceivers with optical fibre.

• Four wavelength channels were simultaneously modulated at 8 Gb s⁻¹ per channel, achieving error-free or low-error-rate performance.

• The average power per channel at the receiver photodiodes was −19.5 dBm, with a maximum recorded bit error rate (BER) of 6 × 10⁻⁸.

7. Discussion and Future Directions:

• The paper concludes that this scaled-up array of 80 channels on a single 3D-integrated transceiver demonstrates the promise of integrated photonic chips for low-power AI computing.

• The high performance is attributed to the large number of channels, low-capacitance bonding, co-designed electronic-photonic circuits, and advanced devices.

• Future improvements could involve developing resonant modulators and photodiodes with even lower capacitance and higher efficiency. Moving to more advanced CMOS nodes could further reduce electronic circuit energy consumption.

• While the demonstrated bonding technology is highly dense, further scaling might be achieved through hybrid bonding techniques. However, the authors note that further reductions in bond capacitance beyond what they achieved may have diminishing returns.

• Reducing chip-to-fibre optical losses and utilising chip-scale microcombs could further improve energy efficiency and bandwidth.

• The authors also acknowledge the temperature and polarization sensitivity of silicon resonators and suggest the need for thermal control and polarization management circuits.

• The potential applications of this technology extend beyond AI computing to enable pervasive device connectivity and transform computing through optically linked, disaggregated, and reconfigurable resources.

This research presents a significant advancement in inter-chip communication by leveraging dense 3D photonic-electronic integration. The demonstrated high bandwidth, ultra-low energy consumption, and high density of channels offer a promising solution to the data transfer bottleneck in future AI computing systems and potentially other high-performance computing applications. The compatibility with standard CMOS fabrication processes enhances the potential for widespread adoption of this technology.

The primary motivation for this research.

The primary motivation for this research, as highlighted in the paper, stems from the growing demands of artificial intelligence (AI) hardware and the limitations of existing inter-chip data communication methods in meeting these demands.

Here's a breakdown of the key aspects of this motivation:

• The increasing computational power of AI relies on vast distributed networks of advanced semiconductor chips. This necessitates the efficient transfer of large volumes of data between these chips.

• However, a significant barrier to scaling AI is the disproportionately high energy and chip area required to transmit data between these chips. The current electrical interconnects face limitations in terms of both bandwidth and energy efficiency.

• The paper explicitly states that a critical bottleneck to the full implementation of light-based communication for computing is the conversion of electrical data from inside a computer chip to optical data. Currently, data is sent out of chips through relatively long electrical wires before reaching optical transmitters, which are often in the form of pluggable optical transceivers.

• These limited electrical channels and their wire lengths result in data rates that are not scalable without accounting for a substantial amount of energy consumption. This data transfer bottleneck hinders the progress and scaling of future AI computing hardware.

• Therefore, the researchers were motivated to find a solution to this "long-standing overhead" by developing a more efficient and scalable way to transmit data between chips. Their approach focuses on dense three-dimensional (3D) integration of photonics and electronics to condense electrical channels and convert them to optical signals within a compact area.

• The goal is to eliminate the bandwidth bottleneck between spatially distinct compute nodes and support the scaling of future AI computing hardware through ultra-energy-efficient, high-bandwidth data communication links.

Therefore the primary driving force behind this research is the need to overcome the limitations of traditional electrical interconnects in terms of energy consumption and bandwidth, which are becoming increasingly critical as AI hardware demands more and more efficient inter-chip communication for scaling computational power. The researchers see light as a medium with the unique ability to transmit volumes of data with minimal energy loss, and their work aims to bring this capability to inter-chip communication in a highly integrated and efficient manner.

Audio Overeview of 3D Photonic Integration for Ultra-Low-Energy Interchip Links

Below we now delve into the fabrication process of this highly innovative 3D photonic-electronics CMOS chip integration. It is a quite impressive and important read!

The fabrication process for the transceiver assembly

The fabrication process for the transceiver assembly involves several key steps, as detailed in the "Methods" section of the paper.

1. Separate Fabrication of Electronic and Photonic Chips:

• The electronic and photonic chips are fabricated using separate CMOS foundries.

• The photonic chips are produced through the American Institute for Manufacturing Integrated Photonics (AIM) on custom 300-mm silicon-on-insulator wafers. Their process design kit includes the microdisks, ring filters, and photodiodes.

• The electronic chips are fabricated through Taiwan Semiconductor Manufacturing Company Limited (TSMC) on a shared multi-project wafer in a 28-nm CMOS process node.

2. Post-Fabrication Processing:

• Both types of chips undergo post-fabrication processing before they are bonded together.

• The 300-mm photonic wafer is cored to a 200-mm wafer.

• A wafer-level process is used to bump the pads on the photonic wafer with electroplated layers of copper and tin.

• The electronic chips, received as individual 1.6 mm² units, are processed at the chip level. This involves electroless nickel plating, followed by an additional layer of immersion gold plating to prevent nickel oxidation.

3. Bonding the Photonic and Electronic Chips:

• The bumped photonic wafer is diced into 6.5 mm × 3 mm chips.

• A thermo-compression bond is then used to connect the bumped photonic chips to the plated electronic chips, aligning their pad arrays. This high-density bonding process uses copper pillar bumps with a 15 µm spacing and 10 µm bump diameters (25 µm pitch).

4. Electrical Connections:

• To power and operate the transceiver, electrical connections are made to the electronic chip through the bonds to the photonic chip.

• The metal layers on the photonic chip route these connections to large electrical pads on an exposed edge of the photonic chip.

• Wire bonds are used to connect these pads to a printed circuit board (PCB). The PCB provides connections to:

  • A microcontroller for programming the electronic chip.

  • Power sources for the electronic chip voltage rails.

  • A radio-frequency (RF) clock generator for the 5 GHz clock of the electronic chip.

5. Optical Coupling:

• Optical fibres couple light to waveguide buses through silicon nitride edge couplers.

• These couplers are located on the side of the photonic chip opposite the wire-bond pads.

• A micropositioner is used to align a standard single-mode fibre v-groove array with the edge couplers, which are spaced at a 127 µm pitch.

6. Assembly Locations:

• The assembly procedures were conducted at various locations:

  • Photonic wafer bumping and bonding: Micross AIT.

  • Electronic chip plating: CVI.

  • Wire bonding: Cornell University.

This multi-step process combines advanced lithography for chip fabrication with precise post-fabrication processing and bonding techniques to create the 3D-integrated photonic-electronic transceiver.

Outline of the benefits of 3D photonic integration for AI scaling

Three-dimensional (3D) photonic integration offers several key benefits for scaling artificial intelligence (AI) hardware:

• Reduced Energy Consumption: A major barrier to AI scaling is the high energy cost of transmitting data between chips. The presented 3D photonic integration platform achieves ultra-low energy consumption for inter-chip communication, with state-of-the-art energy efficiencies of 50 fJ per bit for the transmitter and 70 fJ per bit for the receiver front ends operating at 10 Gb s⁻¹ per channel. This significantly reduces the power overhead associated with data transfer, a critical factor for large-scale AI systems.
  

• Increased Bandwidth: AI applications demand high data transfer rates between compute nodes. The 3D photonic integration platform demonstrates high bandwidth, achieving 800 Gb s⁻¹ with its 80 photonic transmitters and receivers. This increased bandwidth alleviates the bandwidth bottleneck that currently limits the scaling of AI computing hardware.
  

• Enhanced Density of Interconnects: The 3D integration allows for a much greater number of integrated channels compared to prior demonstrations, achieving an order-of-magnitude improvement. With 80 channels occupying a combined chip footprint of only 0.3 mm², the platform reaches a high 3D channel density of 5.3 Tb s⁻¹ mm⁻². This dense integration is crucial for connecting the vast distributed networks of advanced semiconductor chips required for AI.
  

• Overcoming Electrical Interconnect Limitations: Current methods rely on centimetre-long electrical wires to move data out of compute chips before interfacing with optical transceivers. These electrical channels have a limited number and wire lengths, resulting in data rates that are not scalable without high energy consumption. 3D photonic integration addresses this by condensing electrical channels and converting them into optical signals within a compact area on-chip, thus bypassing the limitations of traditional electrical interconnects.
  

• Flexibility in Technology Nodes: Unlike monolithic integration where photonic devices and CMOS transistors are on the same chip, 3D integration combines a more efficient, leading-edge CMOS node electronic chip with a separate photonic chip. This allows the electronics to benefit from advancements in CMOS technology (e.g., smaller node sizes for better energy efficiency and speed) without being constrained by the requirements of the photonic devices.
  

• Relaxed Signal Processing Requirements: Having a large array of many low-data-rate channels (10 Gb s⁻¹ per channel in this demonstration) can relax signal processing and time multiplexing of the low-data-rate streams native to processors. This can simplify the overall system design and potentially reduce complexity and power in other parts of the AI hardware.
  

In summary, 3D photonic integration offers a pathway to create ultra-energy-efficient, high-bandwidth data communication links that are essential for overcoming the current bottlenecks in inter-chip communication and enabling the continued scaling of future AI computing hardware. The increased density, reduced energy per bit, and higher aggregate bandwidth provided by this technology are crucial for realising the full potential of distributed AI systems.

Concluding Remarks

Based on this research, the concluding remarks highlight the significant potential of dense three-dimensional (3D) photonic integration to address the critical challenges in scaling artificial intelligence (AI) hardware.

• The primary motivation for this work was the disproportionately high energy and chip area required for inter-chip data transfer in AI systems, which poses a significant barrier to scaling. The current reliance on electrical interconnects faces fundamental limitations in bandwidth and energy efficiency.
  

• To overcome these limitations, the researchers developed a novel 3D photonic-electronic transceiver featuring an unprecedented density of 80 channels on a single chip. This was achieved through advanced fabrication processes, including the separate fabrication of electronic (28-nm CMOS) and photonic chips, followed by a high-density copper pillar bonding technique.
  

• This 3D integration offers several key benefits for AI scaling, including ultra-low energy consumption (50 fJ/bit for the transmitter, 70 fJ/bit for the receiver), high bandwidth (800 Gb s⁻¹), and a high density of 3D channels (5.3 Tb s⁻¹ mm⁻²). This approach effectively bypasses the bottlenecks associated with traditional electrical interconnects and allows for more efficient and scalable data communication between compute nodes.
  

• Furthermore, the 3D integration approach offers flexibility in technology nodes, allowing the electronic chip to leverage leading-edge CMOS technology for improved performance without constraining the photonic components. The large number of low-data-rate channels also relaxes signal processing requirements.
  

• The successful demonstration of a complete low-power, high-bandwidth data communication link between two transceivers further validates the potential of this technology for next-generation computing systems.
  
  

Looking ahead, the researchers note that while the demonstrated system achieves record performance, there is potential for further improvements through advancements in modulator and photodiode design, the use of more advanced CMOS nodes, and the development of even denser bonding technologies. Addressing challenges such as chip-to-fibre optical losses, temperature sensitivity of resonators, and polarization sensitivity will also be important for future implementations.

In conclusion, this research provides a compelling demonstration of how dense 3D photonic integration can unlock the potential of light for ultra-energy-efficient, high-bandwidth inter-chip communication. This breakthrough offers an immediate solution to the pressing challenge of AI scaling and could have far-reaching implications for future computing architectures, enabling pervasive device connectivity and transforming computing through optically linked, disaggregated resources.